Info: Starting NativeLink simulation with ModelSim-Altera software Quartus sim root : /opt/Altera/intelFPGA_lite/17.0/quartus/eda/sim_lib Quartus root : /opt/Altera/intelFPGA_lite/17.0/quartus/linu圆4/ Info: NativeLink has detected Verilog design - Verilog simulation models will be used Info: Start Nativelink Simulation process IOW, you can't keep the dialog box open to help find the file, you have to make note of where the file is, close the dialog box, then open the file. Meaning you have to make the dialog box go away before you can open the file it tells you to check for more information. where the error message says to check for more details) are only populated after you hit OK.
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